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NCV8851 Automotive Grade Synchronous Buck Controller
The NCV8851 is an adjustable output, synchronous buck controller, which drives dual N-channel MOSFETs, ideal for high power applications. Average current mode control is employed for very fast transient response and tight regulation over wide input voltage and output load ranges. The IC incorporates an internal fixed 6.0 V low-dropout linear regulator (LDO), which supplies charge to the switch mode power supply's (SMPS) bottom gate driver, limiting the power lost to excess gate drive. The IC is designed for operation over a wide input voltage range (4.5 V to 20 V) and is capable of 10 to 1 voltage conversion at 500 kHz. Additional controller features include undervoltage lockout, internal soft start, low quiescent current sleep mode, programmable frequency, SYNC function, average current limiting, cycle-by-cycle overcurrent protection and thermal shutdown.
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TSSOP-20 SUFFIX DB CASE 948E
MARKING DIAGRAM
NCV 8851 ALYWG G
* * * * * * * * * * * * * *
Average Current Mode Control 0.8 V 2% Reference Voltage Input Voltage Range of 4.5 V to 20 V 6.0 V Low-dropout Linear Regulator (LDO) Input UVLO (Undervoltage Lockout) Internal Soft-start 1.0 mA Maximum Quiescent Current in Sleep Mode Adaptive Non-overlap Circuitry 150 ns Minimum High-side Gate Off-time Programmable Fixed Frequency - 170 kHz to 500 kHz External Clock Synchronization up to 600 kHz Average Current Limiting (ACL) Cycle-by-Cycle Overcurrent Protection (OCP) Thermal Shutdown (TSD)
NCV8851 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
Device NCV8851DBG NCV8851DBR2G Package TSSOP-20 (Pb-Free) TSSOP-20 (Pb-Free) Shipping 75 Units/Rail 2500/Tape & Reel
Applications
* Automotive Systems Requiring High Current * Pre-regulated Supply for Low-voltage SMPSs and LDOs
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2010
April, 2010 - Rev. 2
1
Publication Order Number: NCV8851/D
NCV8851
VIN 12 EN 11 VIN_IC SYNC 3 1 Fixed-Frequency Oscillator Ramp Clock Max Duty S Enable TSD Fault UVLO Logic LDO ILIMIT + VREF
9
6VOUT
ROSC 20
LDO Enable Fault Soft Start VSS
4 5
BST GH VSW
Min On Time R Q Reset Dominant PWM Fault CCOMP 15 CEA CFB 16 CSOUT 17 VCOMP 14 VFB 13 VEA + VREF OCP VOCP + BST
Q
6 Nonoverlap 6VOUT 7 8 2 CSA + ACL VACL
GL PGND VIN_CS
19 CSP 18 CSN
VSS
10 AGND
VCLAMP
Figure 1. Functional Block Diagram
VIN VIN EN VIN_IC SYNC ROSC ROSC 6VOUT DBST 4 5 6 7 8 CCOMP CC1 RC1 CFB RC2 CSOUT 2 19 18 16 17 10 AGND 13 14 BST Q1 GH VSW Q2 GL PGND VIN_CS CSP CSN VFB CV2 VCOMP RV1 CV1 RF0 RF1 1W 4300 pF + VIN - CBST L RS C + VOUT +
12 11 3 1 20
9
+
-
15
CC2
Figure 2. Application Schematic
Note: This part is recommended for synchronous use only.
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NCV8851
PACKAGE PIN DESCRIPTIONS - 20 Lead TSSOP
Package Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Symbol SYNC VIN_CS VIN_IC BST GH VSW GL PGND 6VOUT AGND EN VIN VFB VCOMP CCOMP CFB CSOUT CSN CSP ROSC External clock synchronization input. Supply input for the internal current sense amplifier. Supply input for internal logic and analog circuitry. Supply input for the floating top gate driver. An external diode, DBST, from 6VOUT and a 0.1 mF to 1 mF capacitor, CBST, to VSW forms a boost circuit. Gate driver output for the external high-side NMOS FET. Switch-node. This pin connects to the source of the high-side MOSFET and drain of the low-side MOSFET. This pin serves as the switch output to the inductor. Gate driver output for the external low-side NMOS FET. Power Ground. Ground reference for the high-current path including the NMOS FETs and output capacitor. Output of internal fixed 6.0 V LDO. Analog Ground. Ground reference for the internal logic and analog circuitry as well as ROSC and the compensators. Enable input. When disabled, the LDO, internal logic and analog circuitry and gate drivers enter sleep mode, drawing under 1 mA. Supply input for the SMPS. SMPS's voltage feedback. Inverting input to the voltage error amplifier. Connect to VOUT through a resistive divider. SMPS's voltage error amplifier output and non-inverting input to the current error amplifier. SMPS's current error amplifier output and inverting input to the PWM comparator. SMPS's current feedback. Inverting input to the current error amplifier. Single-ended output of the differential current sense amplifier. Connect to CFB through a resistor. Non-inverting input to the cycle-by-cycle overcurrent comparator. Differential current sense amplifier inverting input. Differential current sense amplifier non-inverting input. Oscillator's frequency adjust pin. Resistor to ground sets the oscillator frequency. Function
MAXIMUM RATINGS (Voltages are with respect to AGND unless otherwise indicated.)
Rating Dc Supply Voltage (VIN) Peak Transient Voltage (Load Dump, EN = 0 V) Dc Supply Voltage (VIN_CS) Dc Supply Voltage (VIN_IC) Pin Voltage (VSW) t 50 ns Pin Voltage (BST, GH) Pin Voltage (GL) Pin Voltage (EN) Pin Voltage (CSP, CSN) Pin Voltage (VFB, VCOMP, CSOUT, CFB, CCOMP, SYNC, ROSC, 6VOUT) Pin Voltage (PGND) Operating Junction Temperature Storage Temperature Range Peak Reflow Soldering Temperature: Lead-free 60 to 150 seconds at 217C Value -0.3 to 20 45 46 6.5 -0.7 to 40.7 -2 46 wrt PGND 7 wrt VSW -0.3 to 7 wrt PGND -0.3 to 40 -0.3 to 10 -0.3 to 7 -0.3 to 0.3 -40 to 150 -65 to 150 265 peak Unit V V V V V V V V V V C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCV8851
ATTRIBUTES
Characteristic ESD Capability (All Pins) Human Body Model Machine Model Charge Device Model Package Thermal Resistance Junction-to-Ambient, RqJA (Note 1) Junction-to-Ambient, RqJA (Note 2) 1. 50 mm2, 1.0 oz copper on FR4 board. 2. 500 mm2, 1.0 oz copper on FR4 board. Value 1.5 kV 200 V 1.0 kV 156C/W 108C/W
ELECTRICAL CHARACTERISTICS
(-40C < TJ < 150C, 4.5 V < VIN < 20 V, 4.5 V < BST < 46 V, ROSC = 51.1 kW, unless otherwise specified) Characteristic GENERAL Quiescent Current (IVIN + IVIN_CS + IBST) VIN = 13.2 V, EN = 0 V, Sleep Mode -40C < TA < 125C VIN = 13.2 V, VFB = 1 V EN = 5 V, No Switching VIN = 13.2 V, VFB = 0 V EN = 5 V, Switching LDO Current Thermal Shutdown Thermal Shutdown Hysteresis Undervoltage Lockout (VIN_IC) Undervoltage Lockout Hysteresis SWITCHING REGULATOR Reference Voltage Minimum GH Off Time Minimum GH Pulse Width OSCILLATOR Switching Frequency ROSC = 51.1 kW ROSC = 23.2 kW ROSC = 16.2 kW 153 306 425 0.9 170 360 500 1.1 187 414 575 1.3 kHz kHz kHz V Static Operating 0.784 80 - 0.8 150 140 0.816 220 200 V ns ns VIN = 13.2 V, VFB = 0 V, EN = 5 V Switching, 3.3 nF on GH and GL Guaranteed by Design Guaranteed by Design VIN_IC increasing - - - - 150 - 4.1 50 - 2.0 3.2 10 180 10 4.3 125 1 3.0 5.0 20 210 20 4.5 200 mA mA mA mA C C V mV Conditions Min Typ Max Unit
Ramp Voltage Amplitude VOLTAGE ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Charge Currents Guaranteed by Design Guaranteed by Design Source, VCOMP = 0 V Sink, VCOMP = 1.75 V FB Bias Current CURRENT SENSE AMPLIFIER Common-Mode Range Amplifier Gain 0 (CSP-CSN) 100 mV 1.2 V CSN 10.0 V Guaranteed by Design
70 8.0 2 1.3 -
73 10 4 3 0.1
- - - - 1.0
dB MHz mA mA mA
1.2 -
- 1
10.0 -
V V/V
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NCV8851
ELECTRICAL CHARACTERISTICS
(-40C < TJ < 150C, 4.5 V < VIN < 20 V, 4.5 V < BST < 46 V, ROSC = 51.1 kW, unless otherwise specified) Characteristic CURRENT ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Charge Currents Guaranteed by Design Guaranteed by Design Source, CCOMP = 1.75 V Sink, CCOMP = 1.75 V FB Bias Current Clamping Voltage CURRENT LIMIT Average Current Limit Threshold Cycle-by-Cycle Current Limit Threshold Voltage Cycle-by-Cycle Current Limit Response Time Cycle-by-Cycle and Average Current Limit Threshold Difference SYNC SYNC Frequency Range SYNC Pin Bias Current SYNC Threshold Voltage 6.0 V LDO Output Voltage Dropout Voltage Current Limit GATE DRIVERS GH Sink Current GH Source Current GL Sink Current GL Source Current GH to GL Delay GL to GH Delay SOFT START Time ENABLE (EN) Input Threshold Input Current Logic Low Logic High EN = 2.0 V - 2.0 - - - 3.0 0.8 - 10 V mA FSW = 170 kHz - 14 - ms VGH = 2 V, VIN_IC = 6 V, Guaranteed by Design VGH = 4 V, VIN_IC = 6 V, Guaranteed by Design VIN_IC = 6 V VGL = 1.0 V Guaranteed by Design VIN = 13.2 V VIN = 13.2 V - - - - - - 1.5 1.5 1.5 1.5 40 40 - - - - 70 70 A A A A ns ns IOUT = 20 mA IOUT = 20 mA 5.8 - 30 6.0 - 75 6.2 200 120 V mV mA VSYNC = 0 V VSYNC = 5.0 V Logic Low Logic High FSW - - - 2.0 - 0.1 10 - - 600 0.2 20 0.8 - kHz mA V Guaranteed by Design 1.2 V CSN 10.0 V 80 115 - 20 100 165 200 - 125 215 - - mV mV ns mV Guaranteed by Design 70 8.0 2 1.3 - 2.7 73 10 4 3 0.1 3.5 - - - - 1.0 - dB MHz mA mA mA V Conditions Min Typ Max Unit
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NCV8851
TYPICAL CHARACTERISTICS
(TA = +25C, VIN = 13.2 V, ROSC = 51.1 kW, unless otherwise noted)
100% 4.0 20 Top Gate Bottom Gate
90%
3.5
18
80%
Soft Start Time (%)
2.5
Fall Time (ns)
220 270 320 370 420 470
70%
Driver Current (mA)
3.0
16
14
60%
2.0
12
50%
40%
1.5
10
30% 170 220
1.0
8
Switching Frequency (kHz)
270
320
370
420
470
170
Switching Frequency (kHz)
0
1
2
3
4
Load Capacitance (nF)
Figure 3. Soft-start Time vs. Frequency
38 Top Gate Bottom Gate
Figure 4. Driver Quiescent Current vs. Frequency
105% Switching No Switching
Figure 5. Driver Fall Time vs. Load Capacitance
1
33
95%
0.8
Operating Current (%)
28
85%
Shutdown Current (A)
-50 0 50 100 150
Rise Time (ns)
0.6
23
75%
0.4
18
65%
13
55%
0.2
8 0
45%
0 -50 0 50 100 150
Load Capacitance (nF)
1
2
3
4
Ambient Temperature (C)
Ambient Temperature (C)
Figure 6. Driver Rise Time vs. Load Capacitance
101%
Figure 7. Operating Quiescent Current vs. Temperature
101%
Figure 8. Sleep Mode Quiescent Current vs. Temperature
100.5%
Average Current Limit Threshold (%)
99%
99%
Switching Frequency (%)
-50 0 50 100 150
100%
Cycle-by-Cycle OCP Threshold (%)
100% 100.0%
99.5%
98%
98% -50 0 50 100 150
97%
99.0% -50
Ambient Temperature (C)
Ambient Temperature (C)
Ambient Temperature (C)
0
50
100
150
Figure 9. Average Current-Limit Threshold vs. Temperature
Figure 10. Cycle-by-Cycle Overcurrent Protection Threshold vs. Temperature
Figure 11. VREF vs. Temperature
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NCV8851
TYPICAL CHARACTERISTICS
(TA = +25C, VIN = 13.2 V, ROSC = 51.1 kW, unless otherwise noted)
102%
170 kHz 360 kHz 500 kHz
70 65
GH to GL
GL to GH
108%
101%
60 55 50
106%
Minimum Pulse Width (%)
-50 0 50 100 150
Switching Frequency (%)
100%
104%
Delay (ns)
99%
45 40 35 30 25
102%
98%
97%
100%
96% -50 0 50 100 150
20
98% -50 0 50 100 150
Ambient Temperature (C)
Ambient Temperature (C)
Ambient Temperature (C)
Figure 12. Oscillator Frequency vs. Temperature
100.50%
Figure 13. Non-Overlap Delay vs. Temperature
1000 UNSTABLE
Figure 14. GH Minimum Pulse Width vs. Temperature
130 120 110 100 90 80 70 60 50
()
100.25%
100
Output Capacitor ESR
6V OUT (V)
STABLE 10
100.00%
99.75%
1
UNSTABLE (0.1uF only)
99.50% 0.00
0.1 5.00 10.00 15.00 20.00
LDO Load Current (mA)
0
5
10
15
20
Dropout Voltage (mV)
-50
0
50
100
150
LDO Load Current (mA)
Ambient Temperature (C)
Figure 15. LDO Load Regulation
Figure 16. LDO Stability Region
Figure 17. LDO Dropout Voltage vs. Temperature
100
93%
80
60
Efficiency (%)
40
20
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Load Current (A)
Figure 18. Efficiency vs. Load Current 5 V, 170 kHz Demo Board
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NCV8851
DETAILED OPERATING DESCRIPTION
General
The NCV8851 is a synchronous buck controller with internal 1.5 A gate drivers designed to drive NMOS FETs. The internal gate drivers simplify design, improve performance and efficiency and minimize board area. The controller uses an 800 mV, 2.0% reference, allowing for a wide range of precise output voltage programmability. The NCV8851 also provides a programmable fixed frequency range of 170 kHz to 500 kHz, allowing more design flexibility in compromising efficiency versus components' size and cost. This frequency is conveniently set with an external resistor to ground. An external clock signal can also be used to synchronize the NCV8851 to a higher operating frequency during operation. To protect against possible damage of external power-stage components, excessive inrush of current during start-up is prevented by an internal soft-start, and
inductor current is limited via average current limiting (ACL) and cycle-by-cycle overcurrent protection (OCP). Thermal shutdown (TSD) is also implemented to protect the device from overheating.
Average Current Mode Control
The NCV8851 employs an average current mode control (ACMC) architecture to regulate the output voltage. ACMC uses two loops, as seen in Figure 19. Through the current error amplifier (CEA), the inner current loop monitors the inductor current with the unity gain current sense amplifier (CSA). The current loop responds to input voltage changes, affecting the line transient response. Using the voltage error amplifier (VEA), the outer voltage loop monitors the output voltage, responding to output load changes, affecting the load transient response. Feedback resistors in the voltage loop select the output voltage.
Outer Voltage Loop
VSW PWM and Gate Drivers
L Inner Current Loop
RS
VOUT
C CSA Gain=1 + - RL
VEA
Figure 19. ACMC Loops
Unlike voltage mode control (VMC) of buck regulators, which almost always require the extra components of a Type-III compensation network for adequate transient response, ACMC buck regulators use Type-II compensation. This greatly simplifies the compensator design and optimization process, while offering much faster transient response than a Type-I compensation network. Additionally, the two-loop system separates the effects of output components between the two loops, further simplifying the compensation process. Type-II compensation places a zero and two poles in each of the error loops to offset the effects of the inherent open-loop response. This compensation requires a resistor and two capacitors in the feedback loop for each of the error
amplifiers, shown as complex impedances in Figure 19. An input resistor from the CSA to the CEA sets the gain of the CEA. The voltage loop also has a pair of feedback resistors from VOUT to set the output voltage and gain of the VEA.
Enable
The enable input (EN) is a TTL-compatible input used to activate the internal LDO. The NCV8851 is disabled when the EN pin is pulled below the enable input logic low threshold voltage, causing a normal shutdown to occur, putting the part into a low quiescent current sleep mode. When the EN pin is pulled above the enable input logic high threshold voltage, the part is enabled, the LDO output is brought up and then the internal soft-start begins.
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- + VREF
CEA
- +
NCV8851
VIN
REN EN Internal Enable DZEN1 5.4 V
125 k DZEN2 22 V
to support the internal rails and power the controller. The IC will start up when enabled and VIN_IC surpasses the UVLO threshold and will shutdown when VIN_IC drops below the UVLO threshold minus the UVLO hysteresis. While VIN is less than the set point for VOUT, the output will run at max duty cycle, after soft-start, once VIN_IC surpasses the UVLO threshold. If EN is high and not tied to VIN, the output will begin to rise up while in UVLO, if a minimum output load of 1 kW is not met.
Thermal Shutdown
Figure 20. Enable Pin Equivalent Structure
The EN pin can be tied to VIN in order to enable the part. If EN is above 22 V, DZEN2 will be conducting, as well as DZEN1. The current to DZEN1 is limited by an internal 125 kW resistor. If DZEN2 is conducting, it is recommended at least 250 mA is pulled through this diode. The resistor REN must be used if VIN can go above 20 V as follows.
R EN(max) + VZ 250 mA
The NCV8851 provides Thermal Shutdown (TSD), which monitors the die temperature and turns off the top and bottom gate drivers if an over temperature condition is detected, for added protection. The internal soft-start capacitor is also discharged. A normal soft-start will occur when the die temperature falls below the TSD threshold minus the TSD hysteresis.
Duty Cycle and Maximum Pulse Width Limits
Where VZ is the amount of volts where DZEN2 is conducting, but not yet supplied with 250 mA. For example, setting VZ to 1 V means REN must be less than 4 kW for DZEN2 to have at least 250 mA when VIN is at least 23 V; for the range of VIN between 22 V and 23 V, DZEN2 will be conducting, but not with the recommended 250 mA current.
UVLO
In steady state dc operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. There is a built in minimum off-time which ensures that the bootstrap supply is charged every cycle, determining the maximum duty cycle at a given frequency. The NCV8851 can achieve at least a 95% duty cycle while operating at frequencies up to 200 kHz (89% at up to 500 kHz).
Internal Soft-Start
Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN_IC is too low
The NCV8851 features an internal soft-start function, which reduces inrush current and overshoot of the output voltage. Figures 21 and 22 show a typical soft-start sequence.
VIN UVLO Threshold 6VOUT and VIN_IC
Soft-start Time VSW 90%*VOUT t 10%*VOUT
VOUT t
Figure 22. Switch-node in Soft-Start
Soft-start Delay
Figure 21. Normal Start-up
Soft-start is achieved by ramping up the internal soft-start voltage (VSS), which is applied to the non-inverting input of the voltage error amplifier, effectively limiting the slew rate of VOUT rising. This ramp is generated by charging an internal soft-start capacitor based on the internal oscillator,
causing the soft-start time to be inversely related to the frequency set by ROSC. The internal soft-start capacitor is discharged when the part is disabled, enters TSD or enters UVLO, ensuring a proper start-up when the part is re-enabled, leaves TSD or leaves UVLO.
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NCV8851
This sequence begins once VIN_IC surpasses its UVLO threshold when the part is enabled and the LDO output has risen. After an initial delay to assure a clean start-up, switching begins, the output initially rises quickly and then rises monotonically. The duty cycle is gradually increased until VOUT has reached its set point or until maximum duty cycle is reached.
Normal Shutdown Behavior and Sleep Mode
Normal shutdown occurs when the IC stops switching because the input supply drops below the UVLO threshold, the part enters TSD or the part is disabled. When disabled, the part enters sleep mode. In sleep mode, the LDO turns off and its output capacitor discharges, causing switching to stop, the internal soft-start capacitor to discharge and GH and GL to go low. The switch node enters a high impedance state and the output inductor and capacitors discharge through the load. The supply current reduces to the sleep mode quiescent current.
Internal Linear Regulator (LDO)
The 6VOUT pin should be externally connected through a diode to the BST pin, charging the BST capacitor during off-time to generate a voltage for the high-side driver. When the part is enabled and VIN is below the LDO regulated value, the LDO is in dropout and it tracks VIN. The LDO regulates its output once VIN is above the output set point plus the dropout voltage. An external bypass capacitor must be connected from 6VOUT to ground. A short to ground or overcurrent condition on the 6VOUT pin will be mitigated by the LDO current limit and internal thermal shutdown (TSD) circuitry which disables all outputs. A normal soft-start will occur when the die temperature falls below the TSD threshold.
Drivers
The NCV8851 has an onboard low-dropout linear regulator (LDO) internally connected to drive the low-side gate. The 6VOUT pin should be externally connected to the VIN_IC pin to power the internal rails. Typically, a RC filter is used from 6VOUT to VIN_IC to further decrease noise on the internal rails.
The NCV8851 includes 1.5 A gate drivers to switch external N-Channel MOSFETs. This allows the NCV8851 to address high-power, as well as low-power conversion requirements. The gate drivers also include adaptive non-overlap circuitry. The non-overlap circuitry increases efficiency, which minimizes power dissipation, by minimizing the body diode conduction time, while protecting against cross-conduction (shoot-through) of the MOSFETs. A detailed block diagram of the non-overlap and gate drive circuitry used in the chip and related external components is shown in Figure 23.
BST MainFault GL to GH Delay GL Threshold GH to GL Delay Main Fault VSW Threshold 6VOUT GL PGND GH VSW VSW
PWM Output
Figure 23. Gate Driver Block Diagram
A capacitor is placed from VSW to BST and a diode is placed from 6VOUT to BST to create a bootstrap supply on the BST pin for the high-side floating gate driver. This ensures that the voltage on BST is about 6VOUT higher than VSW, less a diode drop, yielding a gate drive voltage high enough to enhance the high-side MOSFET. The BST capacitor supplies the charge used by the gate driver to charge up the input capacitance of the high-side MOSFET, and is typically chosen to be at least a decade larger than this capacitance. A 0.1 mF BST capacitor is recommended.
Since the BST capacitor only recharges when the low-side MOSFET is on, pulling VSW down to ground, the NCV8851 has a minimum off-time. This also means that the BST capacitor cannot be arbitrarily large, since 6VOUT needs to be able to charge it up during this minimum off-time so the high-side gate driver doesn't run out of headroom. 6VOUT needs to supply charge both to the BST capacitor and also the low-side driver, so the LDO capacitor must be sufficiently larger than the BST capacitor. A 1 mF LDO capacitor is recommended.
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NCV8851
Careful selection and layout of external components is required to realize the full benefit of the onboard drivers. The capacitors between VIN and GND and between BST and VSW must be placed as close as possible to the IC. The current paths for the GH and GL connections must be optimized, minimizing parasitic resistance and inductance.
Current Limiting and Overcurrent Protection
The NCV8851 contains average current limiting (ACL) and cycle-by-cycle overcurrent protection (OCP) to protect the power switches, inductor, current sense resistor and other external components. The current through the inductor is continuously sensed using the CSP and CSN pins. A sense resistor is placed between these pins to translate the output current to a proportional voltage. This voltage is compared to a fixed internal voltage threshold. When the differential voltage exceeds the ACL threshold, the PWM pulse is terminated for this cycle, limiting the current through the inductor. In steady-state operation, decreasing the load resistance while in ACL will cause the duty cycle and VOUT to decrease proportionally without skipping pulses or jitter. There is also a fast OCP path which is tripped when the differential voltage exceeds the OCP threshold, which is
above the ACL threshold. This causes the PWM pulse to be terminated very quickly and disables the part from switching back on until the current through the inductor has dropped below the OCP threshold. Once the inductor current is below the OCP threshold, the part will begin switching again and the current will be limited by ACL, until the inductor current drops below the ACL threshold. An advantage of this current limiting scheme is that the NCV8851 will limit large transient currents yet resume normal operation on the following cycle. Additionally, the current will not run away, nor will the part latch off in case of a short, which is typical of other current limiting schemes employing high-side current sensing.
SYNC Feature
An external clock signal can synchronize the NCV8851 to a higher frequency. The rising edge of the SYNC pulse turns on the power switch to start a new switching cycle, as shown in Figure 24. There is a 0.5 ms delay between the rising edge of the SYNC pulse and rising edge of the VSW pin voltage. The SYNC threshold is TTL logic compatible, and duty cycle of the SYNC pulses can vary from 10% to 90%. The SYNC frequency must be higher than the internal oscillator frequency set by ROSC.
Figure 24. Synchronization from 170 kHz to an external 600 kHz signal Snubber
A snubber consisting of a 4300 pF ceramic capacitor and a 1 W reistor from switch node to ground is required to decrease noise susceptibility. The resistor should be rated for
0.5 W of power dissipation for switching frequencies below 280 kHz and 1 W of power dissipation for switching frequencies above 280 kHz. The snubber should be placed close to the switch node pin.
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NCV8851
APPLICATIONS INFORMATION
Design Methodology
Choosing external components for the NCV8851 encompasses the following design process: 1. Define operational parameters 2. Select switching frequency 3. Select current sensor 4. Select output inductor 5. Select output capacitors 6. Select input capacitors 7. Select compensator components
(1) Operational Parameter Definition
Before proceeding with the rest of the design, certain operational parameters must be defined. These are application-dependent and include the following: VIN: input voltage, range from minimum to maximum with a typical value [V] VOUT: output voltage [V] IOUT: output current, range from minimum to maximum with initial start-up value [A] ICL: desired typical current-limit [A] A number of basic calculations must be performed up-front to use in the design process, as follows:
V OUT D MIN + V IN(max) D+ V OUT V IN(typ) V OUT V IN(min)
leading to decreased efficiency, especially noticeable at light loads. Typically, the switching frequency is selected to avoid interfering with signals of known frequencies. Often, in this case, the frequency can be programmed to a lower value with ROSC and then a higher-frequency signal can be applied to the SYNC pin to increase the frequency dynamically to avoid given frequencies. A spread spectrum signal could also be used for the SYNC input, as long as the lowest frequency in the range is above the programmed frequency set by ROSC. Additionally, the highest SYNC frequency must not exceed maximum switching frequency limits. There are two limits on the maximum allowable switching frequency: minimum off-time and minimum on-time. These set two different maximum switching frequencies, as follows:
F SW(max)1 + F SW(max)2 + 1 * D MAX T MinOff D MIN T MinOn
D MAX +
Where: FSW(max)1: maximum switching frequency due to minimum off-time [Hz] TMinOff: minimum off-time [s] FSW(max)2: maximum switching frequency due to minimum on-time [Hz] TMinOn: minimum on-time [s] Alternatively, the minimum and maximum operational input voltage can be calculated as follows:
V IN(min) + V IN(max) + V OUT 1 * T MinOff @ F SW V OUT T MinOn @ F SW
Where: DMIN: minimum duty cycle (ideal) [%] VIN(max): maximum input voltage [V] D: typical duty cycle (ideal) [%] VIN(typ): typical input voltage [V] DMAX: maximum duty cycle (ideal) [%] VIN(min): minimum input voltage [V] It should be noted that these are the ideal duty cycles; the actual duty cycles will be marginally higher than these calculated values. The actual duty cycles are dependent on load due to voltage drops in the MOSFETs, inductor and current sensor.
(2) Switching Frequency Selection
Where: FSW: switching frequency [Hz] The switching frequency is programmed by selecting the resistor connected between the ROSC pin and ground. The grounded side of this resistor should be directly connected to the AGND pin. Avoid running any noisy signals under the resistor, since injected noise could cause frequency jitter. The graph in Figure 25 shows the required resistance to program the frequency. From 150 to 450 kHz, the following formula is accurate to within 3%:
R OSC + 8687000 F SW
Selecting the switching frequency is a trade-off between component size and power losses. Operation at higher switching frequencies allows the use of smaller inductor and capacitor values to achieve the same inductor current ripple and output voltage ripple. However, increasing the frequency increases the switching losses of the MOSFETs,
Where: ROSC: frequency program resistor [W] Some specific values for switching frequency with standard 1% resistors can be seen in Table 1.
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NCV8851
600 500 400 300 200 100 0 10 20 30 40 50 60 70 80 90
ROSC (kW)
Figure 25. Frequency vs. ROSC Table 1. Frequency vs. ROSC
FSW (kHz) 170 250 300 360 500 ROSC (kW) 51.1 34.8 28.7 23.2 16.2
smaller physical size. Since the inductor is often one of the largest components in the power supply, a minimum inductor value is particularly important in space- constrained applications. From an electrical perspective, an inductor is chosen for a set amount of current ripple and to assure adequate transient response. Larger inductor values limit the switcher's ability to slew current through the output inductor in response to output load transients, impacting the dynamic response. While the inductor is slewing current during this time, output capacitors must supply the load current. Therefore, decreasing the inductance allows for less output capacitance to hold the output voltage up during a load step. Load transient simulation is a powerful tool in anticipating this response. For switchers with both cycle-by-cycle overcurrent protection (OCP) and average current limiting (ACL), the OCP and ACL references are compared to the sensed current via sense resistance, RS. A minimum inductance is required to prevent the OCP from tripping during the onset of ACL during typical operation as follows:
L MIN + V OUT(1 * D) RS @ 2 @ F SW DV CL
FSW (kHz)
Where: LMIN: minimum inductance to assure OCP and ACL do not both trip [H] DVCL: difference between OCP and ACL threshold voltages [V] For switchers that use the current signal of the inductor for control purposes, the voltage ripple over the sense resistance must be sufficient in magnitude to counteract the contribution due to inherent comparator offsets and other errors, as follows:
L MAX + V OUT @ (1 * D MAX) RS @ F SW E L @ V CL
The soft-start time can be estimated as follows:
T SS [ F0 @ T SS0 F SW
Where: TSS: soft-start time [s] F0: specified frequency [Hz] TSS0: soft-start time at specified frequency [s]
(3) Current Sensor Selection
Current sensing for average current mode control relies on the inductor current signal. This is translated into a voltage via a current sensor, which is then measured differentially by the current sense amplifier, generating a single-ended output to use as a control signal. The easiest means of implementing this transresistance is through the use of a sense resistor in series with the output inductor and capacitors. A sense resistor should be selected as follows:
V R S + CL I CL
Where: LMAX: maximum inductance to assure adequate voltage ripple over the sense resistance [H] L: inductor current ripple to current limit ratio [%] VCL: threshold voltage for the current limit [V] The inductor current ripple to current limit ratio is expressed as follows:
EL + iL I CL
Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desired current limit [A] Alternative methods, such as lossless inductor current sensing, are feasible but beyond the scope of this document.
(4) Output Inductor Selection
As a rule of thumb, ensuring that L is at least 5% to 10% has been empirically sufficient. Smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current, which causes higher output voltage ripple. The peak-to-peak ripple current is given by the following equation:
iL + V OUT @ (1 * D) L @ F SW
Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to
Where: iL: peak-to-peak output current ripple [App]
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NCV8851
The ripple current is at a maximum when the duty cycle is at a minimum value and vice versa, as follows:
@ (1 * D MIN) V i L(max) + OUT L @ F SW i L(min) + V OUT @ (1 * D MAX) L @ F SW (5) Output Capacitor Selection
Where: iL(max): maximum inductor current ripple [App] iL(min): minimum inductor current ripple [App] From this equation it is clear that the ripple current increases as L decreases, emphasizing the trade-off between dynamic response and ripple current. The peak and valley values of the triangular current waveform are as follows:
iL 2 i I L(vly) + I OUT * L 2 I L(pk) + I OUT )
The output capacitor is a basic component for the fast response of the power supply. During a load step, for the first few microseconds, it supplies the current to the load. The controller immediately recognizes the load step and increases the duty cycle, but the current slope is limited by the inductor's slew rate. During a load release, the output voltage will overshoot. The capacitance will dampen this undesirable response, decreasing the amount of voltage overshoot. In the case of stepping into a short, the inductor current approaches zero with the worst case initial current at the current limit and the initial voltage at the output voltage set point, calculating the voltage overshoot as follows:
DV OS + L @ I CL 2 ) V OUT 2 * V OUT C
Where: IL(pk): peak (maximum) value of ripple current [A] IL(vly): valley (minimum) value of ripple current [A] Saturation current is specified by inductor manufacturers as the current at which the inductance value has dropped a certain percentage from the nominal value, typically 10%. For stable operation, the output inductor must be chosen so that the inductance is close to the nominal value even at the peak output current, IL(pk). It is recommended to choose an inductor with saturation current sufficiently higher than the peak output current, such that the inductance is very close to the nominal value at the peak output current. This introduces a safety factor and allows for more optimized compensation. Inductor efficiency is another consideration when selecting an output inductor. Inductor losses include dc and ac winding losses and core losses. Core losses include eddy current losses, which are very low due to high core resistance, and magnetic hysteresis losses, which increase with peak-to-peak ripple current. Core losses also increase as switching frequency increases. Ac winding losses are based on the ac resistance of the winding and the RMS ripple current through the inductor, which is much lower than the dc current. The ac winding losses are due to skin and proximity effects and are typically much less than the dc losses, but increase with frequency. Dc winding losses account for a large percentage of output inductor losses and are the dominant factor at switching frequencies at or below 500 kHz. The dc winding losses in the inductor can be calculated with the following equation:
P L(dc) + I OUT 2 @ R dc
Accordingly, a minimum amount of capacitance can be chosen for a maximum allowed output voltage overshoot:
C MIN + L @ I CL 2 (V OUT ) DV OS(max)) 2 * V OUT 2
Where: CMIN: minimum amount of capacitance to minimize voltage overshoot to DVOS(max) [F] DVOS(max): maximum allowed voltage overshoot during a short [V] A maximum amount of capacitance can be found based on the inrush current and current limit. To calculate the input startup current, the following equation can be used:
I INRUSH + C OUT @ V OUT ) I OUT(i) t SS
Where: IINRUSH: input current during startup IOUT(i): initial output current If the inrush current is higher than the steady-state input current with the maximum load, then the input fuse should be rated accordingly, if one is used. During soft-start, the inductor current must provide current to the load, as well as current to charge the output capacitor. The maximum current which the inductor is allowed to conduct is the current limit. Setting the inrush current to the current limit, this puts a limit on the maximum capacitor size, as follows:
C MAX + (I CL * I OUT(i)) @ t SS V OUT
Where: PL(dc) : dc winding losses in the output inductor Rdc: dc resistance of the output inductor (DCR) As can be seen from the above equation, to minimize inductor losses, an inductor with very low DCR should be chosen.
Where: CMAX: maximum output capacitance [F] Capacitors should also be chosen to provide acceptable output voltage ripple with a dc load, in addition to limiting voltage overshoot during a dynamic response. Key specifications are equivalent series resistance (ESR) and equivalent series inductance (ESL). The output capacitors must have very low ESL for best transient response. The PCB traces will add to the ESL, but by putting the output capacitors close to the load, this effect can be minimized and ESL neglected in determining output voltage ripple.
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NCV8851
The capacitance itself causes a voltage ripple due to the current ripple. This is as follows:
VQ + iL @ D C @ F SW
Where: vQ: output voltage ripple due to output capacitance [Vpp] Also, the ripple current through the inductor causes a voltage ripple over the output capacitor due to its ESR as follows:
V ESR + i L @ R ESR
capacitors must be rated to handle a ripple current of one-half the maximum output current at the switching frequency. ESR is the majority cause of losses in the input capacitors. Losses in the input capacitors can be calculated with the following equation:
P CIN + I IN(RMS) 2 @ R ESR(CIN)
Where: vESR: output voltage ripple due to the effects of ESR [Vpp] RESR: total ESR of output capacitors [W] Typically, the ripple due to ESR dominates, having the largest effect on output voltage ripple. The total output voltage ripple in steady-state operation can be calculated as follows:
V OUT + V Q ) V ESR + E C @ V OUT
Where: PCIN = power loss in the input capacitors RESR(CIN) = effective series resistance of the input capacitance Due to large current transients through the input capacitors, electrolytic, polymer or ceramics should be used. If a tantalum must be used, it must be surge protected, to prevent against capacitor failure. Due to the large ripple current, it is common to put small ceramic capacitors in parallel with the bulk input capacitors, which will handle a significant portion of the ripple current. A value of 0.01 mF to 0.1 mF placed near the MOSFETs is recommended.
(7) Compensator Design
Where: vOUT: total output voltage ripple [Vpp] C: percent output voltage ripple [%] Typically, the voltage ripple percentage is a performance parameter used to decide on the desired output capacitor. The maximum total effective ESR of the output capacitors is calculated as follows:
R ESR(max) + V OUT * V Q i L(max)
Where: RESR(max): maximum allowable total ESR of output capacitors It should be noted that these values of ESR are at the switching frequency and ESR decreases as frequency increases. The steady-state power lost due to the ESR of the output capacitor can be calculated as follows:
P C(ESR) + 1 i L 2 @ R ESR 3 (6) Input Capacitor Selection
The input capacitors have to sustain the ripple current produced during the on time of the high-side MOSFET and must have a low ESR to minimize the losses. The RMS value of this ripple is:
I IN(RMS) + I OUT D @ (1 * D)
Where: IIN(RMS) = input RMS current The large majority of the ripple spectrum will be at the switching frequency. The above equation reaches its maximum value with D = 0.5, IIN(RMS) = IOUT/2. The input
The purpose of the compensators is to stabilize the dynamic response of the converter. By optimizing the compensators, stable regulation with fast input line and output load transient response is achieved. Compensator design is related to the placement of zeros and poles in the closed loop, in order to assure stability with optimized transient response. The general approach is to use some rule of thumb values and then tune them through simulation to optimize load step response, while assuring stability over line and load variations. Type-II compensators are used with the two error amplifiers in average current mode control. The CEA closes the inner current-loop and the VEA closes the outer voltage-loop. As a rule of thumb, a zero is placed in each loop with the intent to compensate the effects of the double pole from the output inductor and capacitor. Additionally, a pole is placed at origin, due to the negative feedback, and a pole is also placed in each loop with the intent to compensate the effects of the double right-half-plane zero from the current sampling function. The crossover frequency is then set so that gain limitations of the error amplifier are not exceeded. The compensator must assure there is adequate phase margin in the total closed-loop response, which can be analyzed on a small-signal basis. Further reduction in loop gain, via decreasing the crossover frequency, may be required to avoid large-signal clamping limitations; this effect can be seen in simulation and taken care of in the compensator tuning process.
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NCV8851
Equations for placement of pole, zero and crossover frequency follow:
Current-loop Compensator Voltage-loop Compensator
w iz + w ip +
1 L@C
w vz + w vp +
2 L@C
F SW @ p 4
F SW @ p 4
w i + 2 @ w ip
w v + 2 @ w vp
The implementation of the above compensators is through a resistance on the negative input (RC2, RV2), resistor (RC1, RV1) and capacitor (CC1, CV1) in series in feedback and another capacitor (CC2, CV2) in feedback of an opamp. The
Current-loop Compensator
feedback capacitors (CC1, CV1) in series with feedback resistor are chosen, on the order of less than 3 nF. The values are calculated as follows:
Voltage-loop Compensator
R C1 + C CE +
1 w iz @ C C1 1 w ip @ R C1 C C1
C C C1 CE
R V1 + C VE +
1 w vz @ C V1 1 w vp @ R V1 C V1
C C V1 VE
C C2 + R C2 +
*1
C V2 +
*1
1 w i @ (C C1 ) C C2)
R V2 +
1 w v @ (C V1 ) C V2)
The resistance on the negative input of the VEA (RV2) also sets the output voltage. This resistance comprises a resistor divider with a resistor from the output voltage to the negative input of the VEA (RF1) and a resistor from the negative input of the VEA to ground (RF0). The resistor values are calculated as follows:
R F1 + V OUT @ R V2 V REF
P TG + Q TG @ F SW @ V BST
Where: QTG: total high-side MOSFET gate charge at VBST VBST: BST pin voltage The low-side synchronous rectifier MOSFET gate driver losses are:
P BG + Q BG @ F SW @ V CC
R @ R F1 R F0 + V2 R F1 * R V2 Thermal Considerations
Where: QBG: total low-side MOSFET gate charge at VIN The junction temperature of the controller can then be calculated as follows:
T J + T A ) P IC @ R qJA
The power dissipation of the NCV8851 varies with the MOSFETs used, VIN and the boost voltage (VBST). The average MOSFET gate current typically dominates the control IC power dissipation. The IC power dissipation can be estimated as follows:
P IC + V IN @ I Q ) P HS ) P L
Where: TJ = junction temperature of the IC TA = ambient temperature RqJA = junction-to-ambient thermal resistance of the IC package The package thermal resistance (RqJA) can be obtained from the specifications section of this data sheet and a calculation can be made to determine the IC junction temperature. It should be noted that the physical layout of the board, the proximity of other heat sources such as MOSFETs and inductors and the amount of metal connected to the IC impact the temperature of the device. Use these calculations as a guide, but measurements should be taken in the actual application.
Where: PIC: control IC power dissipation IQ: IC measured supply current (quiescent current) PTG: high-side MOSFET gate driver losses PBG: low-side MOSFET gate driver losses The high-side switching MOSFET gate driver losses are:
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NCV8851
PACKAGE DIMENSIONS
TSSOP-20 CASE 948E-02 ISSUE C
20X
K REF
M
2X
L/2
20
11
J J1 B
L
PIN 1 IDENT 1 10
-U- N
0.15 (0.006) T U
S
A -V-
N F DETAIL E -W-
DIM A B C D F G H J J1 K K1 L M
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT
7.06 1
0.36
16X
16X
1.26
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
NCV8851
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NCV8851/D

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